• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Circuit arrangement for inverters or converters with an intermediate circuit comprising two intermediate circuit capacitors (C1, C2) connected in series between a higher and a lower DC voltage potential (UD +, UD-) of the intermediate circuit. In this case, it is proposed that the two DC link capacitors (C1, C2) each have a switching transistor (T1, T2) connected in parallel, which is in each case connected to a center tap (A) arranged between the two DC link capacitors (C1, C2), and for each a control circuit is provided, wherein the control circuit in each case comprises a comparator (K1, K2) whose output is in each case fed back to the non-inverting input of the respective comparator (K1, K2) and whose inverting input in each case to the mid-point terminal (M) of an intermediate the higher and the lower DC potential (UD +, UD-) of the intermediate circuit connected high-impedance voltage divider is connected, and their supply voltage terminals each via a high-impedance resistor (Rsup) with one of the two DC potentials (UD +, UD-) of the DC link and with the between the two DC link capacitors (C1, C2) arranged Center tap (A) are connected.
    公开号:AT516641A1
    申请号:T50929/2014
    申请日:2014-12-19
    公开日:2016-07-15
    发明作者:Franz Kaiblinger；Rudolf Fehringer
    申请人:Schneider Electric Power Drives Gmbh；
    IPC主号:
    专利说明:

    The invention relates to a circuit arrangement for inverters or converters with a DC link, which comprises two DC link capacitors connected in series between a higher DC voltage potential and a lower DC voltage potential of the DC link, according to the preamble of claim 1.
    Circuit arrangements of the type mentioned are used, for example, in converters which serve in a known manner for the energetic coupling of a plurality of electrical networks on a common DC voltage level. In this case, a network-side AC voltage is converted by means of a rectifier circuit into a DC voltage, which is also referred to as an intermediate circuit voltage, Subsequently, the DC voltage of the DC link is converted by means of an inverter circuit into a desired AC voltage. The electrical energy is stored intermediately in a DC link capacitor, whereby in many applications two DC link capacitors are connected in series. In power electronics, aluminum electrolytic capacitors are generally used for this, since they have a very high power density. Increasingly, however, film capacitors with polypropylene films (PP) are used.
    The consequence of the serial circuit of the capacitors is that different leakage currents of the individual DC link capacitors have a disruptive effect on the desired voltage symmetry. These differences in the leakage currents cause
    Voltage shifts at the center tap, which are integrated over the operating time, which means that due to impermissibly high voltage on each of the two capacitors proper functioning of the inverter can no longer be guaranteed.
    Consequently, a balancing of the DC link capacitors is needed, which keeps the center tap at a constant voltage. One way to keep the voltage at the center tap constant is to parallel to the
    DC link capacitors in each case to switch a high-impedance resistor. This high-impedance resistor compensates for existing voltage imbalances via the leakage currents. A disadvantage of this procedure is the. Occurrence of a permanent power loss. In this case, energy was undesirably taken from all intermediate circuit capacitors and converted into heat, whereby the efficiency of the converter is reduced. In addition, the symmetrizing effect is only comparatively weak.
    Another way to keep the voltage at the center tap constant is, parallel to the DC link capacitors, a circuit of active
    To switch components such as FETs (Field Effect Transistor) or IGBTs (Insulated Gate Bipolar Transistor) and the like, which draws their power from the intermediate circuit voltage. However, this requires a large number of serially connected FETs, which increases the space requirement of the circuit. Furthermore, a current limitation for the FETs is usually required.
    Furthermore, it is known to provide an active compensation circuit with active components, wherein the active components are controlled so that voltage imbalances are reduced at the two DC link capacitors. In this procedure, however, a separate power supply for the active compensation circuit is required. In addition, the power losses due to the active components also increase in symmetrized DC link capacitors.
    It is therefore the object of the invention in a circuit arrangement for inverters or inverters with series-connected DC link capacitors to reduce voltage imbalances on the DC link capacitors, without requiring a separate power supply for equalizing circuits and the like. Furthermore, high power losses, as they occur for example in the parallel connection of high-resistance resistors to the DC link capacitors, are to be avoided.
    These objects are achieved by the features of claim 1. Claim 1 relates to a circuit arrangement for inverters or converters with an intermediate circuit comprising two intermediate circuit capacitors connected in series between a higher DC voltage potential and a lower DC voltage of the intermediate circuit, wherein each of the two DC link capacitors is also referred to as Package parallel connected DC link capacitors can be executed. For this purpose, it is proposed that the two DC link capacitors each have a series connection of a compensation resistor and a switching transistor is connected in parallel, which is respectively connected to a arranged between the two DC link capacitors center tap, and for the switching transistor in each case a switching state of the respective switching transistor controlling control circuit is provided the control circuit in each case comprises a comparator whose output is in each case fed back to the non-inverting input of the relevant comparator and whose inverting input is connected to the mid-point connection of a high-impedance voltage divider connected between the higher and the lower DC voltage of the intermediate circuit, and their supply voltage connections in each case via a high-impedance resistor with one of the two DC potentials of the DC link and with the between the be iden DC link capacitors arranged center tap are connected.
    The control circuits for the switching transistors thus draw their power directly from the intermediate circuit voltage, whereby the supply current required for the operation of the comparator in the μΑ range is ensured via a suitably dimensioned high-impedance resistor or a corresponding resistor chain. The supply voltage terminals of the comparator can be connected to each other via a respective comparator associated Zener diode, which stabilizes the supply voltage. The high-impedance voltage divider supplies at its mid-point connection the input voltage for the inverting input of the comparator. The non-inverting input of the comparator is the output of the comparator. This feedback is also referred to as positive feedback and causes a switching hysteresis of the comparator whose on and off thresholds are determined by the supply voltage. The binary output signal of the comparator is used to drive the respectively associated switching transistor, as will be explained in more detail. In any case, the output signal of the comparator depends on the voltage at the center tap between the two DC link capacitors. If this voltage changes, for example due to increased leakage currents at one of the two DC link capacitors, this change can be detected by means of the comparators and a corresponding output signal can be generated which closes that switching transistor which is assigned to the other DC link capacitor. Thus, this other DC link capacitor is discharged until the voltage distribution of the two DC link capacitors is equal again. Since the circuit arrangement according to the invention remains inactive, as long as the DC link capacitors show no electrical asymmetries and no external power supply is needed, the power consumption of the circuit arrangement according to the invention is negligible. Even in the case that the circuit is active, high power losses are avoided, only occurs in one of the two series connected to the switching transistors balancing resistances dissipation of energy and thus heat release, as will be described in more detail, but relatively small and by the Value of the balancing resistances can be precisely defined.
    The output signal of the comparator represents a binary signal which corresponds to the logic signal "0" at a first value and the logic signal "1" at a second value. This output signal could in principle already for a Ansfeuerung of
    Switching transistors can be used by as the input signal of a separate regulator for the switching transistor determines the switching state of the switching transistor, but not directly drives the switching transistor, When using a FET, in particular a MOSFET, as a switching transistor, the output voltage of the comparator is also suitable for direct gate -Ansteuerung. For this purpose, it is proposed in the context of a first control circuit for a first switching transistor that the control circuit comprises a suitable inverting component with or without switching hysteresis, hereinafter referred to as inverter, whose input is connected to the output of the comparator and whose output is connected to the first switching transistor is, and whose supply voltage terminals are connected via the high-impedance resistor to the higher DC potential UD + of the DC link and connected to the arranged between the two DC link capacitors, wherein the first switching transistor is an N-channel FET. This inverter thus also draws its power supply directly from the intermediate circuit voltage, whereby the supply current required for the operation of the inverter in the μΑ range is ensured via the above-mentioned high-resistance resistor of the comparator. The supply voltage terminals of the inverter can also be connected to one another via the Zener diode assigned to the respective comparator in order to stabilize the supply voltage. The output signal of the comparator is thus inverted by the subsequent inverter, that is set to the logic signal "1" if the output signal of the comparator the logic value "0" corresponded, and set to the logic signal "0" when the output signal of the comparator logic signal "1", the first switching transistor is turned on (conducting) and at a logic signal "0" it remains off (non-conducting) because the N-channel FET used is self-blocking
    An analog control circuit can also be used for the second switching transistor. Even with a second control circuit for the second switching transistor, the control circuit may comprise an inverter whose input is connected to the output of the comparator and whose output is connected to the second switching transistor whose supply voltage terminals via a high-resistance but now with the lower DC potential UD- DC link are connected and connected to the arranged between the two DC link capacitors center tap, wherein it is a P-channel FET in the second switching transistor. Otherwise, the comments on the first control circuit also apply to the second control circuit; in particular, the output signal of the comparator is inverted by the following inverter.
    The two control circuits described above are simple in construction and do not require an external power supply. A practical disadvantage, however, results from the switching technically required use of a P-channel FET in the second control circuit. Instead, it would be desirable to be able to avoid the use of a P-channel FET in the second control circuit and to be able to use a practically more advantageous N-channel FET. Therefore, it is proposed that in a second control circuit for a second switching transistor, an N-channel FET is provided as a second switching transistor whose drain terminal is connected via the compensation resistor and a series-connected capacitor to the center tap between the two DC link capacitors, and the second Control circuit comprises an optocoupler whose optical transmitter is connected on the one hand to the output of the comparator and on the other hand via the
    Balancing resistor to the drain terminal of the N-channel FET, and whose optical receiver is on the one hand connected to the source terminal of the N-channel FET and on the other hand connected to the lower DC potential of the DC link. The voltage at the gate of the N-channel FET is defined by a second switching transistor Zener diode Z3, which is connected to its anode against the lower DC potential of the intermediate circuit UD-, an optocoupler is used in a known manner for transmitting a signal between two galvanically isolated circuits. It consists of an optical transmitter, typically in the form of a light emitting diode (LED), and an optical receiver, such as a phototransistor, both housed in an opaque housing. Since the comparator of the second control circuit is at the potential UDO of the center tap and the N-channel FET is at the lower DC potential UD- of the intermediate circuit, a separation between these two potentials is required. This separation is ensured by the optocoupler. However, the optical transmitter of the optocoupler requires comparatively high currents in the range of a few mA, which are provided by the capacitor until the second switching transistor turns on. From this point on, power is supplied by the compensation resistor via the current.
    In order to ensure that the optical transmitter is switched on, it is further proposed that the optical transmitter is connected to the drain terminal of the N-channel FET via an undervoltage barrier, the undervoltage barrier being connected in parallel with the capacitor. The undervoltage lock is also referred to as "Under Voltage Lock Out" (UVLO) and turns on the second control circuit only when the voltage across the capacitor is above a certain value The capacitor holds after switching on the undervoltage lock the potential on this predetermined and for operation The optical transmitter can thus be switched on reliably, as a result of which the N-channel FET also becomes conductive.
    The invention will be explained in more detail below on the basis of exemplary embodiments with the aid of the enclosed figures. It show here the
    1 shows a converter with two DC link capacitors according to the prior art,
    2 shows a known circuit arrangement for balancing the two DC link capacitors by means of high-resistance resistors,
    3 shows a first embodiment of a circuit arrangement according to the invention,
    4a shows the switching hysteresis of the first comparator K1 according to FIGS. 3 and 5,
    4b shows the switching hysteresis of the second comparator K2 according to FIGS. 3 and 5, and FIGS
    Fig. 5 shows a second embodiment of a circuit arrangement according to the invention.
    First, reference is made to FIG. 1. Fig. 1 shows the circuit diagram of an inverter with a network side 1 and a load side 2. The network-side AC voltage is converted by means of a rectifier circuit 3, in the case shown a half-controlled thyristor, into a DC voltage, which is also referred to as a DC link voltage, hereinafter the DC voltage of the DC link 4 by means of an inverter circuit 5 is converted into a desired AC voltage. The electrical energy is stored intermediately in two series-connected intermediate circuit capacitors Cl, C2.
    As already stated, due to parameter differences of the DC link capacitors C1, C2 voltage shifts occur at the center tap A (see FIG. 2) of the two DC link capacitors C1, C2, which can add up over the operating time and can lead to a proper functioning of the converter Consequently, a balancing of the DC link capacitors C 1, C 2 is required, which keeps the center tap A at a constant voltage
    One way to keep the voltage at the center tap A constant is to connect in parallel to the DC link capacitors Cl, C2 each have a high resistance R, as shown in Fig. 2. This high-resistance resistor R equalizes existing voltage imbalances on the leakage currents. A disadvantage of this procedure is the occurrence of a permanent power loss. In this case, all intermediate circuit capacitors Cl, C2 energy is undesirably removed and converted into heat, whereby the efficiency of the inverter is reduced. In addition, the symmetrizing effect is only comparatively weak.
    To avoid this power loss, a first embodiment of a circuit arrangement according to the invention shown in FIG. 3 is proposed. Fig. 3 shows as well as Fig. 5 in. Compared to Fig. 2, only the two DC link capacitors Cl, C2 and the circuit arrangement according to the invention for balancing the DC link capacitors Cl, C2. The rectifier circuit 3 and the inverter circuit 5 have been omitted for the sake of clarity in Figs. 3 and 5 are not darges.
    The two DC link capacitors C1, C2 are connected in series between a higher DC potential UD + and a lower DC potential UD of the DC link. The middle tap A of the two
    DC link capacitors Cl, C2 is at the potential UDO.
    Parallel to the first intermediate circuit capacitor CI is a first switching transistor TI, in the illustrated embodiment, a self-locking N-channel FET, connected with its source terminal connected to the center tap A, and with its drain terminal via a balancing resistor Rbai with the higher
    DC potential UD +. Parallel to the second DC link capacitor C2, a second switching transistor T2, in. a self-blocking P-channel FET, which is connected with its source terminal to the center tap A, and with its drain terminal via a compensation Waderstand Rbai with the lower DC potential UD- of the intermediate circuit.
    The switching state of the first switching transistor TI is determined via a first control circuit which comprises a first comparator Ki and a first inverter S1 whose supply voltage connections are respectively connected via the high-resistance resistor Rsup with the higher DC potential UD + of the intermediate circuit, and with the center tap A of the two DC link capacitors Cl, C2. The supply voltage terminals of the first comparator Ki and of the first inverter Si are further connected to one another via a first Zener diode Zi associated with the first comparator Ki, which is connected in the reverse direction in the direction of the center tap A.
    The first control circuit for the first switching transistor TI thus draws its power directly from the intermediate circuit voltage. The high-resistance resistor RSUp, which can also be embodied as a chain of a plurality of resistors, has resistance values in the ΜΩ range and is chosen such that the supply current required for the operation of the first comparator Ki in the μΑ range is ensured. The high-resistance connected to the higher DC potential UD + of the DC link supply voltage terminal of the first comparator Ki and the first inverter S1 is thereby at a positive potential of Uv +, about 3V.
    Furthermore, a high-impedance voltage divider consisting of the two high-impedance voltage divider resistors or resistor chains Rdiv is provided, which likewise have resistance values in the ΜΩ range. The voltage divider supplies at its mid-point terminal M the input voltage for the inverting input of the first comparator Ki. At the non-inverting input of the first comparator Ki is the output of the first comparator Ki. This feedback is also referred to as positive feedback and causes a switching hysteresis of the first comparator Ki, whose on and off thresholds are set by the supply voltage Uv. This switching hysteresis is shown in FIG. 4a. For negative values of the input voltage Um, the first comparator Ki supplies an output signal Ua which corresponds to the logic signal "1." If a switch-off threshold Uv + is exceeded, the first comparator Ki supplies an output signal Ua which corresponds to the logic signal "0". The first comparator Ki supplies an output signal Ua which again corresponds to the logic signal "1." The binary output signal Ua of the first comparator Ki is subsequently inverted using the first inverter Si and lies directly at the gate of the latter If the voltage at the gate terminal of the illustrated N-channel FET is greater than its threshold voltage, it will turn on and become conductive.
    The switching state of the second switching transistor T2 is determined via a second control circuit comprising a second comparator K2 and a second inverter S2, whose supply voltage connections are connected via the high-resistance resistor Rsup to the lower DC potential UD- of the intermediate circuit, as well as with the center tap A of two DC link capacitors Cl, C2. The supply voltage terminals of the second comparator K2 and the second inverter S2 are across the second one
    Comparator K2 associated second Zener diode Z2 connected to each other, which is connected in the direction of the center tap A in the reverse direction.
    The second control circuit for the second switching transistor T2 thus draws its power directly from the intermediate circuit voltage. As already mentioned, the high-resistance resistor RSUp has resistance values in the ΜΩ range and is chosen such that the supply current required for the operation of the second comparator K2 in the μΑ range is ensured. The high-resistance connected to the lower DC potential UD of the DC link supply voltage terminal of the second comparator K2 and the second inverter S2 is thereby at a negative potential of Uv-, about -3V.
    The high-impedance voltage divider consisting of the two high-impedance voltage divider resistors Rdiv with resistance values in the ΜΩ range supplies at its mid-point terminal M and the input voltage for the inverting input of the second comparator K2. At the non-inverting input of the second comparator K2, the output signal Ua of the second comparator K2 is applied. This feedback in turn causes a switching hysteresis of the second comparator K2, whose on and off thresholds are set by the supply voltage Uv. This switching hysteresis is shown in FIG. 4b. With positive values of the input voltage Um, the second comparator K2 supplies an output signal Ua which corresponds to the logic signal "1." If the voltage drops below a switch-off threshold Uv-, the second comparator K2 supplies an output signal Ua which corresponds to the logic signal "0". Only when a switch-on threshold Uvo is exceeded does the second comparator K2 supply an output signal Ua which again corresponds to the logic signal "1." The binary output signal Ua of the second comparator K2 is subsequently inverted with the aid of the second inverter S2 and lies directly at the gate of the latter If the voltage at the gate terminal of the illustrated P-channel FET is more negative than its threshold voltage, the second switching transistor T2 turns on and becomes conductive.
    The voltage UDO at the center tap A between the two DC link capacitors CI and C2 is in the ideal case constant, in practice it changes due to electrical asymmetries of the two DC link capacitors CI and C2, occurs in the case of the second DC link capacitor C2 shown in Fig. 3, an increased leakage current on, UDO drops off (AUDO <0). Therefore, the potential at the supply voltage terminals of the first comparator Ki assigned to the first switching transistor TI also decreases. The input voltage Um of the first switching transistor TI associated first comparator Ki is characterized relative to the applied supply voltage positive. Due to the switching hysteresis, however, the output signal of the first comparator Ki does not change immediately, but only when the switch-off threshold Uv + is exceeded, that is to say when the absolute value of the AUDO is greater than Uv + (see FIG. 4a). The output signal Ua of the first comparator Ki takes in this. In this case, a value corresponding to the logic signal "0." This output signal Ua is set to the logic signal "1" by the succeeding inverter Si, and the first switching transistor TI becomes conductive. In physical view, the gate of the first switching transistor TI is at a greater voltage than its source terminal to which the dropped voltage UDO-AUDO of the center tap A is applied. The second comparator Kz, on the other hand, remains at a decrease of UDO (AUD0 <0) an output signal Ua which corresponds to the logic signal "1" (see FIG. 4b), which is set to the logical signal "0" by the subsequent inverter S , leaving the second switching transistor T2 open. In physical terms, the gate Namely connecting the second switching transistor T2, namely the same voltage as its source terminal to which the dropped voltage UDO-AUDO of the center tap A is applied, whereby the P-channel FET used is not conductive.
    Since the first switching transistor TI is now conducting, the first intermediate circuit capacitor CI is subsequently discharged until the voltage drop across the two intermediate circuit capacitors CI and C2 is equal again. With the intermediate circuit voltage kept constant, UDO again increases in this process and the input voltage Um of the first comparator Ki assigned to the first switching transistor TI becomes smaller again relative to the applied supply voltage. Falls below a switch-on threshold Uvo supplies the first comparator Ki an output signal Ua, which again corresponds to the logic signal "1", which is set by the subsequent inverter Si to the logic signal "0" and the first switching transistor TI off again.
    If, on the other hand, an increased leakage current occurs in the first DC link capacitor CI shown in FIG. 3, UDO increases (AUDO> 0). Therefore, the potential at the supply voltage terminals of the first comparator Ki associated with the first switching transistor TI also increases. The input voltage Um of the first switching transistor TI associated first comparator Ki is characterized relative to the applied supply voltage negative. Due to the switching hysteresis, however, the output signal Ua of the first comparator Ki does not change (see Fig. 4a) and remains at a value corresponding to the logic signal "1." This output signal Ua is applied to the logic signal "0" by the following inverter Si "is set, and the first switching transistor TI remains non-conductive. In the physical view, the same voltage is present at the gate of the first switching transistor TI as at its source.
    Connection to which the higher voltage UDO + AUDO of the center tap A is applied The second comparator K2, on the other hand, changes the output signal Ua when the switch-off threshold of Uv is undershot given an increase of UDO (AUD0> 0) and the input voltage Um becoming negative relative to the supply voltage. , ie when AUDI) is greater in magnitude than Uv- (see Fig. 4b). In this case, the output signal Ua of the second comparator K2 assumes a value corresponding to the logic signal "0." This output signal Ua is set to the logic signal "1" by the subsequent inverter S2, and the second switching transistor T2 word is turned on. In physical terms, the gate terminal of the second switching transistor T2 is now at a smaller voltage than its source terminal, at which the higher voltage UDO + AUDO of the center tap A is applied, whereby the P-channel FET used is conductive.
    Since the second switching transistor T2 is now conducting, the second DC link capacitor C2 is subsequently discharged until the voltage drop across the two DC link capacitors CI and C2 is the same again. In this process, UDO becomes smaller again and the input voltage Ihn of the second comparator K2 assigned to the second switching transistor T2 becomes larger again relative to the applied supply voltage. When a switch-on threshold Uvo is exceeded, the second comparator K2 supplies an output signal Ua, which again corresponds to the logic signal "1", which is set to the logic signal "0" by the following inverter S2 and switches off the second switching transistor T2 again.
    The two control circuits described above are in their. Easy to set up and requires no external power supply. As already mentioned, however, a practical disadvantage results from the switching-technically required use of a P-channel FET in the second control circuit. Instead, it would be desirable to be able to avoid the use of a P-channel FET in the second control circuit and to be able to use a practically more advantageous N-channel FET.
    Therefore, according to a preferred embodiment of the invention, a circuit arrangement according to FIG. 5 is proposed. Here, an N-channel FET is provided as a second switching transistor T2, whose drain terminal is connected via a balancing resistor Rbai and a series-connected capacitor C to the center tap A between the two DC link capacitors Cl, C2. The second control circuit further comprises an optocoupler OK whose optical transmitter 6 is connected on the one hand to the output of the second comparator K2 and on the other hand via the compensation resistor Rbai to the drain terminal of the N-channel FET. The optical receiver 7 of the optocoupler OK is on the one hand connected to the source
    Connection of the N-channel FET connected and on the other hand with the lower DC potential UD- of the intermediate circuit. The gate terminal of the N-channel FET is also connected via a the second switching transistor T2 associated third Zener diode Z3 with the lower DC voltage UD- of the intermediate circuit, wherein the second switching transistor T2 associated Zener diode Z3 with its anode with the lower DC potential UD- connected is.
    If an increased leakage current now occurs in the first DC link capacitor CI shown in FIG. 5, UDO initially increases (AUDO> 0). The switching behavior of the first (upper) control circuit is identical to the embodiment according to FIG. 3, so that the corresponding explanations regarding the first control circuit also apply to FIG. With regard to the second (lower) control circuit, due to the increase in UDO, the input voltage Um of the second comparator K2 associated with the second switching transistor T2 becomes more negative relative to the applied supply voltage. The second comparator K2 is now switched so that it has a switching hysteresis according to FIG. 4a. The second comparator K thus changes with an increase of UDO (AUD0> 0) and thus relative to the supply voltage thus negative going input voltage Um, the output signal Ua falls below the turn-on of Uyo (see Fig. 4a). The output signal Ua of the second comparator K2 in this case assumes a value which corresponds to the logic signal "1." This output signal Ua is applied directly to the optical transmitter 6 of the optocoupler OK, which via the compensation resistor Rbai to the drain terminal of the second When the optical transmitter 6 emits light, the optical receiver 7 becomes conductive and the source terminal of the N-channel FET is set to the lower potential UD- of the intermediate circuit. in other words, the second switching transistor T2 becomes conductive whenever the optical transmitter 6 is lit.
    Since the second switching transistor T2 is now conducting, the second DC link capacitor C2 is subsequently discharged until the voltage drop across the two DC link capacitors CI and C2 is the same again. In this process, UDO again becomes smaller and the input voltage Um of the second comparator K2 associated with the second switching transistor T2 becomes more positive again relative to the applied supply voltage. When a turn-off threshold Uv + is exceeded, the second comparator K2 supplies an output signal Ua, which again corresponds to the logic signal "0", which switches off the optical transmitter 6 and thus the second switching transistor T2 again.
    As already mentioned, the optical transmitter 6 of the optocoupler OK requires comparatively high currents in the range of a few mA, which are initially provided by the capacitor C until the second switching transistor T2 turns on, with the result that the supply subsequently takes place via the compensation resistor Rbai. In order to reliably ensure the switching on of the optical transmitter 6, it is further proposed that the optical transmitter 6 is connected to the drain terminal of the N-channel FET via an undervoltage barrier UVLO, the undervoltage barrier UVLO being connected in parallel with the capacitor C. The undervoltage lock UVLO only turns on the second control circuit when the voltage across the capacitor C is above a certain value. The capacitor C holds after switching on the undervoltage lock UVLO the potential on this predetermined and sufficient for the operation of the optical transmitter 6 value. The optical transmitter 6 can thus be switched on reliably, as a result of which the N-channel FET also becomes conductive, thereby ensuring the supply via the resistor Rbai.
    Thus, with a circuit arrangement for inverters or inverters with series-connected intermediate circuit capacitors C 1, C 2, voltage imbalances on the intermediate circuit capacitors C 1, C 2 are reduced without requiring an external power supply for output circuits and the like. Furthermore, high power losses, as they occur for example in the conventional parallel connection of high-resistance resistors to the intermediate circuit capacitors CI, C2, avoided.
    权利要求:
    Claims (7)
    [1]
    claims:
    1. Circuit arrangement for inverters or converters with an intermediate circuit, the two between a higher DC potential (UD +) and a lower DC potential (UD) of the intermediate circuit connected in series intermediate circuit capacitors (Cl, C2), characterized in that the two DC link capacitors (Cl , C2) in each case a series connection of a compensation resistor (Rbai) and a switching transistor (TI, T2) is connected in parallel, which is in each case connected to a between the two DC link capacitors (Cl, C2) center tap (A), and for the switching transistor (TI , T2) in each case a switching state of the respective switching transistor (TI, T2) controlling control circuit is provided, wherein the control circuit in each case comprises a comparator (Κι, K2), the output of each with the non-inverting input of the respective comparator (Κι, K2) is fed back and its inverting input each m it is connected to the mid-point connection (M) of a high-impedance voltage divider connected between the higher and the lower DC voltage potential (UD +, UD-) of the intermediate circuit, and their supply voltage connections in each case via a high-impedance resistor (Rsup) to one of the two DC voltage potentials (UD +, UD-). of the intermediate circuit and with the between the two DC link capacitors (Cl, C2) arranged center tap (A) are connected.
    [2]
    2. A circuit arrangement according to claim 1, characterized in that in a first control circuit for a first switching transistor (TI), the control circuit comprises an inverter (S) whose input is connected to the output of the comparator (K) and whose output to the first switching transistor (TI) is connected, and the supply voltage terminals are connected via the high-impedance resistor (Rsup) to the higher DC potential (UD +) of the intermediate circuit and connected to the between the two DC link capacitors (Cl, C2) arranged center tap (A), wherein it at the first switching transistor (TI) is an N-channel FET.
    [3]
    3. A circuit arrangement according to claim 2, characterized in that in a second control circuit for a second switching transistor (T2), the control circuit comprises an inverter (S) whose input is connected to the output of the comparator (K) and whose output to the second switching transistor (T2) is connected, and whose supply voltage terminals are connected via the high-resistance resistor (Rsup) to the lower DC potential (UD-) of the intermediate circuit and to the between the two DC link capacitors (Cl, C2) arranged center tap (A), wherein the second switching transistor (T2) is a P-channel FET.
    [4]
    4. A circuit arrangement according to claim 1 or 2, characterized in that in a second control circuit for a second switching transistor (T2), an N-channel FET as a second switching transistor (T2) is provided, the drain terminal via the compensation resistor (Rbai) and a series-connected capacitor (C) is connected to the center tap (A) between the two DC link capacitors (Cl, C2), and the second control circuit comprises an optocoupler (OK), the optical transmitter (6) on the one hand to the output of the comparator (K ) and on the other hand via the compensation resistor (Rbai) to the drain terminal of the N-channel FET, and whose optical receiver (7) is connected on the one hand to the source terminal of the N-channel FET and on the other hand to the lower DC potential (UD-) of the DC link is connected.
    [5]
    5. A circuit arrangement according to claim 4, characterized in that the gate terminal of the N-channel FET via a second switching transistor (T2) associated Zener diode (Z3) is connected to the lower DC potential (UD-) of the intermediate circuit, wherein the Zener diode (Z3) is connected to its anode with the lower DC potential (UD-).
    [6]
    6. Circuit arrangement according to claim 4 or 5, characterized in that the optical transmitter (6) via an undervoltage barrier (UVLO) is connected to the drain terminal of the N-channel FET, wherein the undervoltage barrier (UVLO) parallel to the capacitor (C ) is switched.
    [7]
    7. Circuit arrangement according to one of claims 1 to 6, characterized in that the supply voltage terminals of the comparator (K) via a respective comparator (Κι, K2) associated Zener diode (Zi, Z2) are interconnected.
    类似技术:
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    同族专利:
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    AT516641B1|2020-09-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    DE4042378A1|1990-06-23|1992-01-16|Licentia Gmbh|Symmetrical switch discharge system for inverter branch pair - uses gate controlled semiconductor switches connected to DC voltage source|
    DE102006014780A1|2006-03-29|2007-10-18|Schekulin, Ulrich|Direct current regulator for integrated network coupling of photovoltaic generator, has single or multi-phase transformer less inverter provided for coupling photovoltaic generator at direct current voltage intermediate circuit|
    TW201115896A|2009-10-21|2011-05-01|Extech Electronics Co Ltd|Automatic balance circuit capable of dividing DC single voltage source into DC dual voltage source|
    DE102011053013A1|2011-08-26|2013-02-28|Refusol Gmbh|Symmetrical device for balancing voltage division of serially-connected energy storage devices e.g. capacitors, has control unit that drives switch element of bypass circuit according to voltage requirement of energy storage device|WO2022043489A1|2020-08-27|2022-03-03|Keba Industrial Automation Germany Gmbh|Device and method for operating a three-level or multi-level converter|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    ATA50929/2014A|AT516641B1|2014-12-19|2014-12-19|Circuit arrangement for balancing intermediate circuit capacitors|ATA50929/2014A| AT516641B1|2014-12-19|2014-12-19|Circuit arrangement for balancing intermediate circuit capacitors|
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